The present disclosure relates generally to partial reconfiguration integrated circuits, such as field programmable gate arrays (FPGAs). More particularly, the present disclosure relates to initial configuration support for partial reconfiguration implemented for an integrated circuit (e.g., an FPGA).
This section is intended to introduce the reader to various aspects of art that may be related to various aspects of the present disclosure, which are described and/or claimed below. This discussion is believed to be helpful in providing the reader with background information to facilitate a better understanding of the various aspects of the present disclosure. Accordingly, it should be understood that these statements are to be read in this light, and not as admissions of prior art.
Integrated circuits (ICs) take a variety of forms. For instance, field programmable gate arrays (FPGAs) are integrated circuits that are intended as relatively general-purpose devices. FPGAs may include logic that may be programmed (e.g., configured) after manufacturing to provide any desired functionality that the FPGA is designed to support. Thus, FPGAs contain programmable logic, or logic blocks, that may be configured to perform a variety of functions on the FPGAs, according to a designer's design. Some ICs may include adaptable logic that enables partial reconfiguration of the FPGA, such that a portion of the functionality of the IC may be modified (e.g., enabling functionality to be added, removed, and/or swapped) during the runtime of the FPGA.
In digital circuit design, initial conditions are used to express the power-on state of registers and allow the definition of the initial state of the circuit. Register transfer level (RTL) languages such as VHDL and Verilog additionally supply language support to define the initial condition for signals which can then be used by synthesis and simulation. Tool chains, such as Altera Quartus and Xilinx Vivado, may additionally support assignments to express the power-up condition of registers inferred for the target architectures. However, hardware support for initial conditions on registers requires additional area, and as a result initial conditions are not supported in all target architectures and flows. For example, in contrast to ICs which natively support initial conditions by powering up all registers to zero (or other constant value) using special logic at an area cost, ICs designed with area-savings designs that do not provide such native support for initial conditions may power up registers of the partial reconfiguration regions in an undefined state.
When IC architectures do not support the specification of initial conditions on registers in a partial reconfiguration flow, there can be mismatch between synthesis and simulation, which can lead to functional errors in hardware. In these cases and the post-configuration value of registers is unknown, and if not reset to a known state, can cause functional failures. For example, the design may assume that certain initial conditions are present at a register, while the actual initial conditions are unpredictable.